1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to flash Electrically Erasable Programmable Read Only Memory (EEPROM) devices. Even more specifically, this invention relates to an architecture of flash Electrically Erasable Programmable Read Only Memory (EEPROM) devices and a method to read the flash Electrically Erasable Programmable Read Only Memory (EEPROM) devices to reduce column leakage during read.
2. Discussion of the Related Art
A class of non-volatile memory devices known as "flash" EEPROM (Electrically Erasable Programmable Read Only Memory) devices combines the advantages of EPROM density with the electrical erasability of an EEPROM. One feature that distinguishes flash EEPROM memory cells from standard EEPROM memory cells is that unlike standard EEPROM memory cells, flash EEPROM memory cells do not contain a select transistor on a one-for-one basis with each floating gate memory cell. A select transistor is a transistor that allows the selection of an individual memory cell within the memory device and is used to selectively erase a specific memory cell. Because flash EEPROMs do not have a select transistor for each floating gate transistor, flash EEPROM memory cells cannot be individually erased and therefore must be erased in bulk, either by erasing the entire chip or by erasing paged groups or banks of cells. Elimination of the select transistor allows for smaller cell size and gives the flash EEPROM an advantage in terms of manufacturing yield (in terms of memory capacity) over comparably sized standard EEPROMs.
Typically, a plurality of flash EEPROM cells is formed on a semiconductor substrate, which is also known as a silicon wafer. FIG. 1A illustrates a single conventional flash EEPROM memory cell having a double-diffused source region. As shown in FIG. 1, flash memory cell 100 is formed on a p-type substrate 110 and includes an n type double-diffused source region 102 and an n+ drain region 104. The drain region 104 and the source region 102 are spaced apart from each other forming a channel L.sub.CHANNEL 122. A source electrode 114 and a drain electrode 112 are connected to the source region 102 and the drain region 104, respectively. A substrate electrode 105 is connected to the substrate 110.
The double-diffused source region 102 is formed of a lightly doped n region 128 (phosphorous doped) and a more heavily doped but shallower n+ region 130 (arsenic doped) embedded within the deep n region 128. The phosphorus doping within the n region 128 reduces the horizontal electric field between the source region 102 and the substrate 110.
The floating gate 106 is disposed a short distance above the source region 102, the drain region 104 and the channel L.sub.CHANNEL 122, and over a dielectric layer 118, which is also known as a tunnel oxide region. Above the floating gate 106 and disposed over the dielectric layer 116 is a control gate 108. The dielectric layer 116 is typically formed of an oxide/nitride/oxide layer known in the semiconductor manufacturing art as an ONO layer. A control gate electrode 120 is attached to control gate 108. The dimension L.sub.GATE 132 represents the gate length for the gates contained in flash memory cell 100.
In a conventional method of operation, the programming of a flash EEPROM memory cell is achieved by inducing "hot electron" injection from a section of the channel 122 near the drain 104 into the floating gate 106. The injected electrons cause the floating gate 106 to carry a negative charge. Grounding the source region 102, biasing the control gate 108 to a relatively high positive voltage and biasing the drain region 104 to a moderate positive voltage induce the hot electrons.
For example, to program the flash memory cell 100 the source electrode 114 is connected to ground, the drain electrode 112 is connected to a relatively high voltage (typically +4 volts to +9 volts) and the control gate electrode 120 is connected to a relatively high voltage level (typically +8 volts to +12 volts). Electrons are accelerated from source region 102 to drain region 104 via the channel 122 and the "hot electrons" are generated near the drain region 104. Some of the hot electrons are injected through he relatively thin gate dielectric layer 118 and become trapped in the floating gate 106 thereby giving floating gate 106 a negative potential.
After sufficient negative charge accumulates on floating gate 106 the negative potential of floating gate 106 raises the threshold voltage of the stacked gate transistor and inhibits current flow through the channel 122 during a subsequent "read" mode. The magnitude of the read current is used to determine whether a memory cell has been programmed.
Conversely, to erase a flash memory device electrons are typically driven out of the floating gate 106 by biasing the control gate 108 to a large negative voltage and biasing the source region 102 to a low positive voltage in order to produce a sufficiently large vertical electric field in the tunnel oxide. The large vertical field in the tunnel oxide produces Fowler-Nordheim (F-N) tunneling of electrons stored in the floating gate 106 through the tunnel oxide into the source region 102. The charge removed from the floating gate 106 produces a threshold voltage shift.
For example, during erasure a relatively low positive voltage (typically from +0.5 volts to +5 volts) is applied to source electrode 114 and a relatively large negative voltage (typically from -7 volts to -13 volts) is applied to control gate electrode 120. The voltage of the substrate electrode 105 is grounded and the drain electrode 112 is allowed to float. The vertical electric filed established between the control gate 108 and the source region 102 induces electrons previously stored in floating gate 106 to pass through dielectric layer 118 and into source region 102 by way of Fowler-Nordheim tunneling.
In order to produce a sufficient electric field in the tunnel oxide, it is typically necessary to bias the control gate 108 to a large enough negative voltage such that the floating gate 106 reaches a voltage of approximately -5.5 volts. A typical potential difference V.sub.SF between the source region 102 and floating gate 106 is on the order of 10 volts and accordingly, when the source voltage V.sub.s is made less positive the control gate voltage V.sub.CG should be made more negative. Once the source to floating voltage V.sub.SF is selected, the remaining factors are preferably constrained according to the equation: EQU V.sub.FG =.alpha..sub.CG (V.sub.CG -.DELTA.V.sub.T)+.alpha..sub.S V.sub.S +.alpha..sub.B V.sub.B
where:
V.sub.FG =the floating gate voltage; PA1 V.sub.CG =the control gate voltage; PA1 V.sub.S =the source voltage; PA1 V.sub.B =the substrate or p-well bias; PA1 .DELTA.V.sub.T =the threshold voltage difference arising from negative charge added to the floating gate as measured from the control gate; PA1 .alpha..sub.CG =the capacitive coupling coefficient from the control gate to the floating gate; PA1 .alpha..sub.S =the capacitive coupling coefficient between the source and the floating gate; PA1 .alpha..sub.B =the capacitive coupling coefficient between the substrate or p-well and the floating gate.
The cell is read by applying typically 4 to 5 volts to the control gate, approximately 1 volt or less to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (.apprxeq.4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (.apprxeq.2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
To have high enough read current, the voltage at the gate is required to be 4 to 5 volts. Because the source is grounded (0 volts), this relatively large potential difference exists across the tunnel oxide in the vicinity of the source region and causes a stress field across the tunnel oxide in the vicinity of the source region during the duration of the read pulse. Because all of the sources have a common terminal, this stress field is applied across all the bits on the selected wordline. Due to oxide integrity weakness from bit-to-bit, some bits will gain charge and disturb the state of the bits. Blank "1" cells could be programmed and turn to a "0" causing a failure of the flash device after many read cycles. The field across the tunnel oxide is highest close to the source junction. The "thin" tunnel oxide at the source side experiences most of the degradation during cycling, becoming weak thereby allowing conduction through it at lower applied electric fields. In addition, because the bitline to which the cell being read has a voltage applied to it all of the cells connected to that bitline will have a potential difference between the drain and the source because all of the sources are connected to a common terminal. As discussed above, if the threshold voltage of an unselected cell or a number of unselected cells has decreased, the leakage current may mask the expected read current and a faulty read will occur. This will result in failure of the entire memory device.
Therefore, what is needed is a method of reading the memory device to minimize the number of times the relatively large potential difference is applied across each individual cell during read and to decrease the leakage current in the bitlines during read.